17.3 TLB Refill Vector Selection

Address Error Exception

The Address Error exception occurs when an attempt is made to execute one of the following:

• reference to an illegal address space
• reference the supervisor address space from User mode
• reference the kernel address space from User or Supervisor mode
• load or store a doubleword that is not aligned on a doubleword boundary
• load, fetch, or store a word that is not aligned on a word boundary
• load or store a halfword that is not aligned on a halfword boundary

The common exception vector is used for this exception. The AdEL or AdES code in the Cause register is set, indicating whether the instruction caused the exception with an instruction reference, load operation, or store operation shown by the EPC register and BD bit in the Cause register.

When this exception occurs, the BadVAddr register retains the virtual address that was not properly aligned or that referenced protected address space. The contents of the VPN field of the Context, XContext, and EntryHi registers are undefined, as are the contents of the EntryLo register.

The EPC register contains the address of the instruction that caused the exception, unless this instruction is in a branch delay slot. If it is in a branch delay slot, the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set as indication.

Servicing

The process executing at the time is handed a UNIX SIGSEGV (segmentation violation) signal. This error is usually fatal to the process incurring the exception.